DON26BZ05-NV077 — Multi-Core Parallel Processing for Sensor Fusion Architecture
Below is a brief summary. Please check the full solicitation before applying (link in resources section).
Quick Answer
DON26BZ05-NV077 is a Navy Phase I SBIR topic sponsored by NAVAIR. It funds a modular, platform-agnostic sensor fusion architecture using multi-core parallel processing, designed to eliminate track loss and reduce latency in fighter aircraft sensor fusion without falling back on today's data-prioritization filters. Maximum Phase I award across Base and Option is $315,000. Proposals are due September 23, 2026.
Executive Summary
Fusing data from multiple sensors, both homogeneous and heterogeneous, improves target tracking and situational awareness, but current fusion architectures are largely serial, which creates latency and forces a tough tradeoff: to keep up, systems apply a prioritization ranking that processes higher-value tracks while dropping others. That tradeoff risks track loss and incomplete situational awareness for operators, especially in high-workload environments. NAVAIR wants a parallel processing architecture that eliminates that tradeoff entirely rather than optimizing around it.
The architecture needs to decompose fusion tasks (spatial alignment, temporal correlation, attribute fusion) into sub-tasks that run concurrently across multiple processing cores, without losing track integrity to serial bottlenecks or aggressive filtering. Size, weight, and power constraints are specific and non-negotiable: the processing unit needs to fit 5th-generation or later tactical aircraft, typically 0.5 to 1.0 cubic feet at 28VDC power. The design also needs to scale to handle a growing mix of data sources including AESA radar, Distributed Aperture Systems, and Electro-Optical Targeting Systems.
Phase I is architecture and modeling work: define a scalable fusion framework, build a discrete-event simulation to assess throughput, latency, and track correlation accuracy against current serial benchmarks, and map fusion sub-tasks to physical CPU, GPU, or FPGA cores within tactical SWaP constraints. If the Option is exercised, it culminates in a Preliminary Design Document with finalized architectural constraints and a hardware-software roadmap into Phase II.
Phase II has a specific, checkable performance target: approximately a 50 percent reduction in end-to-end track latency compared to Phase I benchmarks, validated through Hardware-in-the-Loop integration on a multi-core System-on-Chip that meets a 28VDC, 80-pound weight envelope, and a real sensor data demonstration. The deliverable is a TRL 6 prototype with a full Test and Evaluation report and transition plan.
Work is expected to become classified in Phase II, requiring a secret facility clearance and personnel clearances. Phase III dual-use applications are broad and specific: search and rescue, home and private security, autonomous driving and robotics, and smart grid and energy management, anywhere multi-sensor fusion under real-time constraints matters.
Funding
Phase I Base: up to $200,000
Phase I Option: up to $115,000
Maximum Phase I total (Base plus Option): $315,000
Award types: Firm Fixed Price, Basic Ordering Agreement, or Prototype Other Transaction
Phase I period: exactly 6 months Base, exactly 6 months Option
Phase II maximum: up to $2,000,000
Discretionary TABA available: up to $6,500 in Phase I, in addition to the award amount
Timeline
Proposal deadline: September 23, 2026
Submission portal: DoW SBIR/STTR Innovation Portal (DSIP)
Notifications sent approximately one week after BAA close
Phase I payments: 50% at 15 days, 35% at 90 days, 15% at 180 days, for both Base and Option
Key Requirements
Technical Volume limited to 10 pages
Minimum two-thirds of Phase I work performed by the proposing small business, in both Base and Option
No cost sharing accepted
CMMC Level 2 (Self) projected requirement
Processing unit must fit 5th-generation tactical aircraft SWaP constraints, 0.5-1.0 cubic feet at 28VDC
Must be able to obtain a secret facility clearance and personnel clearances for classified Phase II work
Point of Contact
Kristi DePriest, Naval Air Systems Command (NAVAIR)
navair-sbir@us.navy.mil
Frequently Asked Questions
What problem does current sensor fusion architecture have?
It's largely serial, creating latency, and to compensate, systems apply prioritization filters that process higher-value tracks while dropping others, risking incomplete tracks and reduced situational awareness.
What specific performance improvement does Phase II target?
Approximately a 50 percent reduction in end-to-end track latency compared to Phase I benchmarks.
What are the size, weight, and power constraints?
The processing unit must fit within 0.5 to 1.0 cubic feet and operate at 28VDC power, compatible with 5th-generation or later tactical aircraft platforms.
What sensor types must the architecture scale to support?
AESA Radar, Distributed Aperture Systems (DAS), and Electro-Optical Targeting Systems (EOTS), among others.
Does this require a security clearance?
Yes. Work is expected to become classified in Phase II, and the contractor must be able to obtain and maintain a secret facility clearance and personnel security clearances.
What TRL does Phase II need to reach?
TRL 6, delivered as a prototype with a comprehensive Test and Evaluation report and transition plan.
Is there a commercial application for this technology?
Yes. NAVAIR points to search and rescue, home and private security, autonomous driving and robotics, and smart grid and energy management as dual-use applications.
How much funding is available in Phase I?
Up to $200,000 for the Base and up to $115,000 for the Option, for a combined maximum of $315,000.
What is the proposal deadline?
September 23, 2026, submitted through the DoW SBIR/STTR Innovation Portal (DSIP).
