OSW26BZ05-DV014: In-Situ Metrology for Mesa-Wall Integrity in Large Format Small-Pixel Infrared Detector Array Fabrication
Below is a brief summary. Please check the full solicitation before applying (link in resources section).
Quick Answer
OSW26BZ05-DV014 is a 2026 OSW-Reliance 21 SBIR topic under the DoW SBIR Program seeking a non-destructive, quick-turn metrology tool that can screen full wafers for surface damage during small-pixel infrared detector array fabrication. Phase I offers a base award of $314,363 over 9 months with a 20-page technical volume limit. A Direct to Phase II track is available at $2,095,748 over 18 months. Proposals are due September 23, 2026 and must be submitted through DSIP.
Overview
The Department of War needs large-format, small-pixel focal plane arrays (FPAs) to support sensor platforms across ground, air, maritime, and space domains. As detector manufacturers push pixel sizes smaller to meet this demand, the fabrication process becomes more fragile. During pixel isolation, mesa-wall surface damage and unwanted surface currents introduce noise that degrades FPA performance and can compromise mission effectiveness.
This topic calls for a prototype instrument that can non-destructively assess mesa-wall integrity across full wafers up to 150mm in diameter, as well as piece parts, at cryogenic temperatures. The tool needs to work across both major detector material systems used in this space: Antimony-based III-V Type-II Superlattice (T2SL) and Mercury Cadmium Telluride (MCT), covering short wave through long wave infrared bands. The government is prioritizing in-situ measurement approaches that let fabricators catch and correct defects during processing rather than after the fact.
Companies with backgrounds in semiconductor metrology, surface current mapping, non-destructive testing, or infrared detector characterization are well positioned here. The solicitation explicitly encourages proposers to partner with prime contractors or commercial T2SL and MCT growth and processing houses, since access to real fabrication environments will matter for a credible Phase II and Phase III transition.
Phase I is about proving the underlying physics and measurement concept, using representative test structures or coupons rather than full production wafers. Phase II scales that concept into a working full-wafer prototype validated against traditional baseline testing at an actual DoW laboratory or FPA fabrication house. Phase III targets integration into IRFPA production lines, with clear relevance to sensors for air, space, maritime, and missile platforms.
Companies pursuing the Direct to Phase II track must already have completed proof-of-concept work independent of any prior federally funded SBIR or STTR Phase I effort, and must document that work thoroughly: technical reports, test data, prototype designs, and performance results.
Funding and Timeline
Phase I base award: $314,363 Phase I period of performance: 9 months Phase I technical volume limit: 20 pages Direct to Phase II award: $2,095,748 Direct to Phase II period of performance: 18 months Direct to Phase II technical volume limit: 20 pages Proposal deadline: September 23, 2026 Submission portal: DSIP only, no other submission method is accepted Additional funding available: Technical and Business Assistance (TABA) funding, up to $6,500 for Phase I awardees and up to $50,000 per Phase II project Critical Technology Area: Quantum and Battlefield Information Dominance CMMC level requirement: Level 1
Who Should Apply
This topic fits small businesses with proven capability in semiconductor surface characterization, cryogenic test instrumentation, or infrared detector fabrication diagnostics. Companies without direct access to T2SL or MCT wafer fabrication should plan to line up a partnership with a growth or processing house before proposing, since the solicitation specifically calls this out as encouraged.
Frequently Asked Questions
What is the deadline for OSW26BZ05-DV014? The proposal deadline is September 23, 2026. Proposals must be submitted through DSIP before the topic closes on that date.
How much funding is available for Phase I? Phase I offers a base award of up to $314,363 for a 9 month period of performance.
Can a company skip Phase I and apply directly for Phase II? Yes. This topic accepts Direct to Phase II proposals, but only from companies that can document completed proof-of-concept work meeting the Phase I objectives, performed independently of any prior SBIR or STTR federal funding.
What materials does the metrology tool need to work with? The tool must be able to assess both Antimony-based III-V Semiconductor Type-II Superlattice (T2SL) and Mercury Cadmium Telluride (MCT) detector materials, across short wave to long wave infrared bands.
Does this topic require a security clearance? Phase I work is expected to be performed at the Unclassified//CUI level, and classified proposals are not accepted. A Phase II contract may require facility and personnel clearances if the work becomes classified.
What size wafers does the system need to measure? The system should accommodate wafers up to 150mm in diameter as well as piece parts.
Who evaluates these proposals? Government technical evaluators may come from Army DEVCOM C5ISR Center, Army DEVCOM Army Research Lab, the Naval Research Laboratory, and the Air Force Research Laboratory.
Is TABA funding available for this topic? Yes. Phase I awardees may request up to $6,500 in TABA funding, and Phase II awardees may request up to $50,000 per Phase II project, using the SBIR/STTR TABA Request Form.
