OSW26BZ05-NV021: Co-packaging Digital Readout Integrated Circuits and Photonics for Advanced Infrared Imaging

Below is a brief summary. Please check the full solicitation before applying (link in resources section).

Quick Answer

OSW26BZ05-NV021 is a 2026 OSW-Reliance 21 SBIR topic under the DoW SBIR Program funding the design and fabrication of a readout integrated circuit with a photonic digital output for infrared sensors operating in cryogenic environments. Phase I offers a base award of $314,363 over 9 months with a 20-page technical volume limit. This topic does not have a Direct to Phase II track. Proposals are due September 23, 2026 and must be submitted through DSIP.

Overview

Modern infrared digital focal plane arrays can generate over 20 gigabits per second of data at standard video framerates in large formats. Getting that bitstream off the sensor in a cryogenic environment is genuinely hard, because it requires balancing electrical, mechanical, and thermal constraints simultaneously. Today's state of practice tops out around 3 gigabits per second per channel at 10 picojoules per bit, and the power that electrical output drivers consume becomes significant enough to shorten cryocooler lifetimes in large-format arrays.

Photonic integrated circuits (PICs) offer a potential 10x or greater improvement in bandwidth, latency, and energy consumption compared to standard electrical input/output approaches. The problem is that every demonstration to date has bolted an off-the-shelf readout integrated circuit (ROIC) to a PIC chiplet on an interposer, which reduces thermal load from wiring but does little to actually reduce overall power consumption. This topic wants a genuinely monolithic solution: either full integration of electronics and photonics on a single silicon wafer, or foundry-level integration of a photonic and electronic layer before detector hybridization, using one of the CMOS/PIC-capable foundries now offering 45 to 180 nanometer processes.

Phase I is about exploring foundry fabrication options for co-packaging or vertically integrating a digital ROIC with photonic chiplets, evaluating feasibility factors like bonding, metallization, planarity, and impurities, and producing an initial PIC design suited to cryogenic operation, along with any needed modifications to existing ROIC designs. Phase II carries this through to full design, tape-out, and fabrication, with cryogenic testing to demonstrate optical output performance, and ideally radiation testing and thermal cycling as well.

This is a strong fit for companies with expertise in photonic integrated circuit design, cryogenic electronics, mixed-signal ROIC design, or foundry-level chip integration. Radiation hardening for space applications is called out as a plus but not a requirement.

Funding and Timeline

Phase I base award: $314,363 Phase I period of performance: 9 months Phase I technical volume limit: 20 pages Direct to Phase II: not available for this topic Proposal deadline: September 23, 2026 Submission portal: DSIP only, no other submission method is accepted Additional funding available: TABA funding, up to $6,500 for Phase I awardees and up to $50,000 per Phase II project Critical Technology Area: Quantum and Battlefield Information Dominance CMMC level requirement: Level 1

Who Should Apply

Companies with photonics design capability, cryogenic mixed-signal electronics experience, or access to CMOS/PIC foundry relationships are the right audience here. This topic rewards proposers who can speak credibly to real foundry integration constraints rather than purely theoretical PIC design.

Frequently Asked Questions

What is the deadline for OSW26BZ05-NV021? The proposal deadline is September 23, 2026. Proposals must be submitted through DSIP before the topic closes.

How much funding is available for Phase I? Phase I offers a base award of up to $314,363 for a 9 month period of performance.

Is Direct to Phase II available for this topic? No. This topic is only open to standard Phase I proposals.

Why does this topic call for monolithic integration instead of chiplet-on-interposer designs? Because chiplet-on-interposer approaches reduce thermal load from wiring but do very little to reduce overall power consumption, which is the actual problem the government is trying to solve for large-format arrays in cryogenic environments.

What data rates is this technology trying to support? State of the art digital infrared focal plane arrays can generate more than 20 gigabits per second, well beyond what current electrical output drivers can handle efficiently in a cryogenic environment.

Is radiation hardening required? No. Design hardening for space and high-radiation environments is called out as advantageous but remains optional for this topic.

What foundry capabilities does this topic assume are available? The topic references several foundries now offering 45 to 180 nanometer CMOS/PIC integration capability as a starting point for proposers.

What is the Phase I deliverable? A comprehensive final report detailing the PIC design, planned ROIC fabrication modifications, and a system integration plan.

Is TABA funding available for this topic? Yes. Phase I awardees may request up to $6,500 in TABA funding, and Phase II awardees may request up to $50,000 per Phase II project.