Part of the DoW SBIR/STTR FY27 Release 2 topic list. Browse all 83 topics by industry or service.
Topic DON27BZ02-DV028 from the DoW SBIR 2027 BAA, Release 2. Pre-release now; proposals due January 6, 2027, 12:00 PM ET.
Quick answer
DON27BZ02-DV028 is a Department of the Navy Direct-to-Phase II SBIR topic, championed by PMW/A 101, seeking a modular FPGA core that separates two-user signal collisions at low SNR and delivers higher-quality likelihoods to soft-decision decoders. Applicants must document feasibility instead of receiving a Phase I award. Proposals are due January 6, 2027, 12:00 PM ET.
Solicitation at a glance
- Topic number: DON27BZ02-DV028
- Official title: DIRECT TO PHASE II: Advanced Multi-User Signal Separation for Tactical Waveforms
- Agency: Department of the Navy
- Program: SBIR (DoW SBIR 2027 BAA, Release 2)
- Award type: Direct to Phase II (no Phase I awards)
- Award amount: Base up to $750,000 (18 months) plus an option up to $1,000,000 (24 months); the option requires 1:1 matching non-SBIR funds. Source: Navy Release 2 instructions in DSIP.
- CMMC level: Level 2 (Self)
- ITAR: Yes. Export-controlled (ITAR/EAR); see topic text
- Technology areas: None
- Pre-release (direct TPOC contact allowed): November 4 to December 2, 2026, 8:00 AM ET
- Opens in DSIP: December 2, 2026, 8:00 AM ET
- Proposals due: January 6, 2027, 12:00 PM ET
- Official source: DSIP Topics app (search DON27BZ02-DV028)
BW&CO's take
What the Department of the Navy wants
In dense tactical networks, friendly transmissions on the same frequency collide, and current receivers treat the overlap as noise and drop the packets. The Navy wants a multi-user separation algorithm that works at very low SNR, generates high-quality Log-Likelihood Ratios for soft-decision FEC decoders, and detects burst collisions to erase or correct corrupted likelihoods. The target is about a 3 dB improvement over the current baseline receiver in two-user collisions. Phase II implements the algorithm in VHDL/Verilog as a modular, open-systems FPGA core, builds an SDR-based hardware testbed, demonstrates real-time separation, and delivers a transition plan toward the MIDS JTRS program of record.
Who is a good fit
- Simulation results (MATLAB, C++, or Python) showing multi-user separation gains near 3 dB in two-user collisions at low SNR
- Strong background in digital signal processing, joint demodulation or other multi-user separation methods, LLR generation, and soft-decision FEC
- Demonstrated FPGA development for high-performance communications, including VHDL/Verilog implementation and resource optimization
- Ability to build SDR testbeds that generate physical two-user collisions and intermittent interference
Watch-outs
- This is Direct-to-Phase II: feasibility documentation must include theoretical analysis, detailed simulation, and performance data substantiating the ~3 dB gain, must not be solely based on prior or ongoing federally funded SBIR/STTR work, and must have been substantially performed by the offeror and/or the PI.
- Phase II work may become classified. The company must be U.S. owned and operated with no foreign influence (unless DCSA-approved mitigation is in place) and able to acquire and maintain a secret level facility and personnel security clearances.
- The Description says the ~3 dB target reflects multi-user separation and decoding performance rather than overall receiver sensitivity, but the Phase III text refers to proving a 3dB receiver sensitivity gain. Consider asking the topic authors which metric governs before direct contact ends December 2, 2026, 8:00 AM ET.
- The topic metadata marks it as ITAR-restricted, which generally limits foreign national participation.
- The topic metadata lists CMMC Level 2 (Self).
Think your company fits DON27BZ02-DV028? Talk with BW&CO before the January 6 deadline.
Plan Your DON27BZ02-DV028 Submission
Official topic text (verbatim from DSIP)
The text in this section is copied word for word from the official DSIP topic as published on November 4, 2026. DSIP is the official source and topics can be amended. Always confirm the current version at dodsbirsttr.mil before you submit. Our commentary above is BW&CO's interpretation, not Government guidance.
Title
DIRECT TO PHASE II: Advanced Multi-User Signal Separation for Tactical Waveforms
Objective
Develop and demonstrate a robust multi-user signal separation for tactical waveforms to improve the quality of likelihoods prior to being processed by soft-decision decoding algorithms.
Description
The Program Office championing this effort is PMW/A 101 that manages and delivers advanced, secure tactical communication systems for naval platforms. A core mandate of this office is to continuously integrate next-generation capabilities that enhance waveform resilience, increase spectral efficiency, and ensure robust connectivity for warfighters operating in highly congested and contested electromagnetic environments. The technology developed under this SBIR Direct to Phase II topic is intended to transition directly into the PMW 101 portfolio of tactical radio systems.
In modern tactical networks, the proliferation of friendly assets creates a dense signal environment where simultaneous transmissions on the same frequency cause multi-user collisions and limit operational effectiveness. This problem is exacerbated in contested domains where very low Signal-to-Noise Ratios (SNRs) are common. Current baseline receiver systems typically treat these overlapping friendly signals as insurmountable noise. Because legacy systems lack the ability to untangle these collisions, they simply drop the packets or fail to decode them entirely, which severely limits network throughput and the real-time data exchange required for mission-critical operations.
To overcome these limitations and maintain a critical operational advantage, this SBIR Direct to Phase II topic seeks the development of an advanced signal processing core capable of robust multi-user signal separation for tactical waveforms. By enabling non-orthogonal multiple access-like schemes, this capability will significantly increase network capacity and user count without requiring additional spectrum.
The goal is to deliver high-quality soft signal likelihoods recovered from simultaneous-user collisions to downstream soft-decision decoding algorithms. To achieve close-to-optimal performance in two-user collisions, proposed approaches must operate effectively at very low SNRs and mitigate intermittent interference by dynamically detecting burst collisions and nullifying compromised likelihood data. While advanced joint demodulation represents one viable pathway, proposers are highly encouraged to suggest any innovative framework that targets an approximate 3dB improvement over current baselines. The targeted improvement will be measured against the current baseline receiver under comparable two-user collision conditions and will reflect improvement in multi-user separation and downstream decoding performance rather than overall receiver sensitivity. This 3dB gain will translate directly to longer communication ranges, higher data rates, and increased resilience against jamming.
This effort requires the performer to:
Develop an advanced algorithm for multi-user separation that is effective in low SNR and interference-prone environments.
Generate high-quality Log-Likelihood Ratios (LLRs) for modern soft-decision forward error correction (FEC) decoders, utilizing novel, proposer-defined technical approaches.
Implement a mechanism to detect burst collisions and erase or correct corrupted likelihood data to prevent decoder failure.
Design, implement, and test the algorithm within a modular Field Programmable Gate Array (FPGA) core based on open-systems principles.
The successful transition of this capability will fundamentally improve the resilience of tactical networks. By delivering a modular FPGA core built on open-systems principles, the solution could be seamlessly integrated into a wide range of current and future Original Equipment Manufacturer (OEM) radio platforms, which could significantly reduce the life-cycle costs associated with developing entirely new systems to achieve these capabilities. This Direct to Phase II effort seeks proposers who can rapidly demonstrate these advanced receiver techniques with a clear transition path into operational military hardware.
Work produced in Phase II may become classified. Note: The prospective contractor(s) must be U.S. owned and operated with no foreign influence as defined by 32 U.S.C. § 2004.20 et seq., National Industrial Security Program Executive Agent and Operating Manual, unless acceptable mitigating procedures can and have been implemented and approved by the Defense Counterintelligence and Security Agency (DCSA) formerly Defense Security Service (DSS). The selected contractor and/or subcontractor must be able to acquire and maintain a secret level facility and Personnel Security Clearances. This will allow contractor personnel to perform on advanced phases of this project as set forth by DCSA and NAVWAR in order to gain access to classified information pertaining to the national defense of the United States and its allies; this will be an inherent requirement. The selected company will be required to safeguard classified material during the advanced phases of this contract IAW the National Industrial Security Program Operating Manual (NISPOM), which can be found at Title 32, Part 2004.20 of the Code of Federal Regulations.
Phase I
Feasibility documentation MUST NOT be solely based on work performed under prior or ongoing federally funded SBIR/STTR work. Demonstrating proof of feasibility is a requirement for a Direct to Phase II award.
For this Direct to Phase II topic, the Government expects that the small business would have accomplished the following:
Vendor must have assessed the feasibility of developing and implementing multi-user signal separation algorithms for tactical waveforms. Prior work should include theoretical analysis, detailed simulation studies (e.g., MATLAB, C++, Python), and performance characterization that substantiates the potential for a ~3dB gain.
Vendor must have demonstrated a strong history of digital signal processing, modern coding/modulation techniques, and FPGA development for high-performance communications systems.
FEASIBILITY DOCUMENTATION: Offerors interested in proposing to this Direct to Phase II topic must include in their response Phase I feasibility documentation that substantiates the scientific and technical merit. The documentation should include technical reports, simulation results, performance data, and analysis of the proposed algorithms. Work submitted must have been substantially performed by the offeror and/or the principal investigator (PI).
Phase II
Develop, implement, and physically demonstrate the multi-user separation algorithms developed in a Phase I-equivalent effort within a tangible hardware environment. Deliver a fully functional FPGA core, integrated into a physical hardware testbed, demonstrating real-time signal separation capabilities. Provide comprehensive design documentation and test reports.
Phase II Tasks
Hardware Implementation: Develop, refine, and decompose the Phase I-equivalent signal separation and likelihood erasure algorithms into hardware-description language (VHDL/Verilog). Implement and optimize the complete algorithm within an FPGA core, balancing performance with resource utilization.
Testbed Construction: Design and assemble a tangible hardware testbed utilizing Software-Defined Radios (SDRs) or equivalent RF hardware capable of generating and receiving physical, two-user signal collisions and intermittent interference at low SNRs.
Real-Time Demonstration: Physically integrate the developed FPGA core with a representative radio system host within the testbed. Conduct a real-time, functional demonstration proving the core's ability to separate colliding signals.
Performance Validation: Develop and execute a comprehensive test plan utilizing the physical testbed. Provide empirical data validating the algorithm's performance against a baseline receiver system, confirming the targeted ~3dB performance improvement.
Documentation Deliverables: Deliver the developed FPGA core files (VHDL/Verilog) alongside a Comprehensive Final Report detailing the hardware architecture, algorithm decomposition, resource utilization metrics, and complete results from acceptance testing.
Transition Strategy: Deliver a comprehensive Phase III Transition Plan detailing the technical milestones, prime OEM partnerships, and programmatic pathways required to transition the modular FPGA core into PMW 101’s tactical radio portfolio, specifically targeting the MIDS JTRS Program of Record.
Work in Phase II may become classified. Please see note in Description section.
Phase III Dual Use Applications
Further develop and validate the modular multi-user separation FPGA IP core on a tactical surrogate testbed in partnership with the OEM to prove a 3dB receiver sensitivity gain. Integrate the validated firmware into the MIDS JTRS (PMW 101) operational flight terminal baseline to support both current and next-generation OEM radio platforms. (Note: Ultimately, this transition pathway enables PMW 101 to deploy the advanced signal-untangling capability across the active fleet via cost-effective, software-defined firmware field upgrades that completely bypass the need for physical hardware redesigns.)
Beyond military acquisition, this technology possesses significant dual-use commercial potential. The ability to successfully separate multi-user signals in highly congested spectrums at low SNRs is a critical requirement for several private-sector markets. The algorithms and FPGA cores developed under this effort can be directly commercialized for:
- 5G/6G Cellular Networks: Improving network capacity, spectral efficiency, and call quality in dense urban environments where signal overlap is frequent.
- Commercial Satellite Communications (SATCOM): Enhancing throughput for Low Earth Orbit (LEO) internet constellations managing thousands of simultaneous user terminals.
References
Viterbi, A.J. "Very Low Rate Convolutional Codes for Maximum Theoretical Performance of Spread-Spectrum Multiple-Access Channels." IEEE Journal on Selected Areas in Communications, vol. 8, no. 4, pp. 641-649, 2002. https://doi.org/10.1142/9789814287517-0012
Wang, X. and Poor, H. V. "Iterative (Turbo) Soft Interference Cancellation and Decoding for Coded CDMA." IEEE Transactions on Communications, vol. 47, no. 7, July 1999, pp. 1046-1061. https://ieeexplore.ieee.org/document/774855
“National Industrial Security Program Executive Agent and Operating Manual (NISP), 32 U.S.C. § 2004.20 et seq. 1993”. https://www.ecfr.gov/current/title-32/subtitle-B/chapter-XX/part-2004
Keywords
Multi-User Detection, Signal Separation, Interference Cancellation, Tactical Waveforms, Field-Programmable Gate Array, FPGA, Soft Decoding, Log-Likelihood Ratio, LLR, Contested Communications
Frequently asked questions
What is DON27BZ02-DV028?
It is a Department of the Navy SBIR topic to develop and demonstrate multi-user signal separation for tactical waveforms, improving the quality of likelihoods passed to soft-decision decoding algorithms, delivered as a modular FPGA core.
When is DON27BZ02-DV028 due?
Proposals are due January 6, 2027, 12:00 PM ET. DSIP pre-release began November 4, 2026, and direct contact with the topic authors is allowed only until the topic opens on December 2, 2026, 8:00 AM ET.
Is this a Phase I or Direct-to-Phase II topic?
It is Direct-to-Phase II. Demonstrating proof of feasibility is a requirement for award, and the feasibility documentation must not be solely based on prior or ongoing federally funded SBIR/STTR work.
How will the 3 dB improvement be measured?
The improvement is measured against the current baseline receiver under comparable two-user collision conditions. It reflects gains in multi-user separation and downstream decoding performance, not overall receiver sensitivity. Phase II must provide empirical testbed data confirming it.