Part of the DoW SBIR/STTR FY27 Release 2 topic list. Browse all 83 topics by industry or service.
Topic DON27TZ02-NV001 from the DoW STTR 2027 BAA, Release 2. Pre-release now; proposals due January 6, 2027, 12:00 PM ET.
Quick answer
DON27TZ02-NV001 is a Department of the Navy STTR topic seeking a co-packaged optics architecture that integrates photonic transceivers with the ROIC of a cryocooled EO/IR sensor to move data from cold to warm space over fiber at high bandwidth and low power. It is a Phase I STTR topic, so a research-institution partner is required. Proposals are due January 6, 2027, 12:00 PM ET.
Solicitation at a glance
- Topic number: DON27TZ02-NV001
- Official title: Co-Packaged Optics (CPO) for Advanced Cryocooled Electro-Optical/Infrared (EO/IR) Sensors
- Agency: Department of the Navy
- Program: STTR (DoW STTR 2027 BAA, Release 2)
- Award type: Phase I (see topic text for Phase II)
- Award amount: Phase I base up to $200,000 plus an option up to $115,000. Source: Navy Release 2 instructions in DSIP.
- CMMC level: Level 2 (Self)
- ITAR: No
- Technology areas: None
- Pre-release (direct TPOC contact allowed): November 4 to December 2, 2026, 8:00 AM ET
- Opens in DSIP: December 2, 2026, 8:00 AM ET
- Proposals due: January 6, 2027, 12:00 PM ET
- Official source: DSIP Topics app (search DON27TZ02-NV001)
BW&CO's take
What the Department of the Navy wants
Reading data electrically out of a cryocooled EO/IR sensor (70 to 140 K) burns power and limits the size, weight, and power of the integrated dewar cooler assembly. The Navy wants commercial co-packaged optics, today built for room-temperature data centers, adapted to sit with the sensor's ROIC and run cold. Proposals must address ROIC compatibility with sub-180 nm analog and mixed-signal designs, thermal management with PIC power under 20 mW, power efficiency, and CMOS-compatible 2.5D/3D packaging. Phase II delivers a working cold-to-warm transceiver prototype tested at 70 to 140 K for bandwidth, energy efficiency, coupling loss, and bit-error rate.
Who is a good fit
- Silicon photonics or PIC design experience, especially low-Vpi modulators and low-loss fiber coupling
- Prior work on cryogenic optical interconnects or cold-to-warm readout for infrared focal plane arrays
- ROIC design or integration knowledge for large-format, fine-pitch sensors
- Access to a PIC foundry and a 2.5D/3D packaging facility that can be named in the Phase II plan
Watch-outs
- This is an STTR topic, so the small business must team with a research institution. The topic text itself does not add further partnering detail.
- Target metrics are specific: PIC power under 20 mW, with example targets of under 10 fJ/bit, over 1 Tbps, and under 0.5 dB coupling loss per fiber connection.
- Phase I must end with a Phase II plan that identifies the PIC foundry and packaging facility, and Phase II must show compatibility with a 640 x 480 or larger ROIC at 10 um pitch or finer.
- The topic requires CMMC Level 2 (Self). It is not marked as ITAR-restricted in the topic metadata.
Think your company fits DON27TZ02-NV001? Talk with BW&CO before the January 6 deadline.
Plan Your DON27TZ02-NV001 Submission
Official topic text (verbatim from DSIP)
The text in this section is copied word for word from the official DSIP topic as published on November 4, 2026. DSIP is the official source and topics can be amended. Always confirm the current version at dodsbirsttr.mil before you submit. Our commentary above is BW&CO's interpretation, not Government guidance.
Title
Co-Packaged Optics (CPO) for Advanced Cryocooled Electro-Optical/Infrared (EO/IR) Sensors
Objective
Develop and demonstrate innovative Co-Packaged Optics (CPO) architectures and integration techniques for advanced cryocooled Electro-Optical/Infrared (EO/IR) sensor systems that significantly reduce the number of electrical wirebonds, increase bandwidth density, and withstand rugged maritime environments for deployment in advanced sensing and tactical edge computing platforms.
Description
Current Department of the Navy (DON) platforms are generating unprecedented volumes of data via advanced radar, SIGINT, and high-resolution imaging sensors. Processing of this data at the tactical edge requires extreme bandwidth but can consume excessive powers, creating significant thermal and signal integrity bottlenecks [Ref 1]. Specifically, for advanced EO/IR sensors that operate in cryocooled temperatures (e.g., 70-140K), the excessive power required to electrically read out the data, i.e., transmit from cold space and receive in warm space, presents a challenging limitation on the size, weight, and power (SWaP) of an integrated dewar cooler assembly. Fiber optics and photonic integrated circuits (PICs) are key optical readout technologies that can offer extreme bandwidth, low power consumption, and mature fabrication but require integrated packaging solutions for next generation DON systems [Ref 2].
CPO offers an integrated solution that considers both optical and electrical elements in EO/IR sensor design, optimizing performance, reliability, and manufacturability. CPO brings the optical transceiver components directly into the same package as the readout integrated circuit (ROIC). This minimizes the electrical channel length or completely eliminates it with photonic interconnects, fundamentally lowering power consumption (energy per bit) and enabling massive bandwidth scaling [Refs 1-4]. To date, commercial CPO solutions are primarily designed for room temperature, climate-controlled hyperscale SI data centers.
This STTR topic seeks to adapt and innovate current CPO technologies for the stringent Size, Weight, Power, and Cost (SWaP-C) and packaging (cryogenically cooled) constraints of advanced Navy EO/IR sensing platforms. The focus of the topic is on the design and development of a CPO architecture that integrates with the ROIC layer of a typical EO/IR sensor chip assembly, enables high-bandwidth cold to warm readout, and operates in cryocooled temperatures.
Proposals must address critical challenges, including:
- ROIC compatibility: PIC interconnect architecture that is compatible with conventional analog and mixed-signal digital ROICs designed in <180 nm node foundries, optimal number of fiber outputs to meet total ROIC bandwidth.
- Thermal Management: Dissipating heat effectively when dense photonics and ROICs are co-located in a cryocooled integrated dewar assembly. Minimize PIC power consumption to less than 20 mW.
- Power Efficiency: Choice of electrical-optical conversion scheme and minimizing power consumption (e.g., half-wave voltage for EO modulators, Vpi), PIC waveguide propagation loss, PIC to fiber input/output coupling losses, and stray light scatter.
- Integration & Packaging: Complementary metal–oxide–semiconductor (CMOS)-compatible substrate materials, 2.5D/3D integration techniques, and cost-effective scalable manufacturing processes.
Phase I
Conduct a feasibility study for a conceptual design of a CPO architecture with full transceiver functionality that addresses the four critical challenges and is tailored for a SWaP-constrained Navy maritime EO/IR sensor system.
- Deliverables: Perform architectural modeling, signal integrity simulations, and thermal/mechanical modeling.
- Metrics: Define target performance metrics, such as energy efficiency (e.g., < 10 fJ/bit), bandwidth (e.g., > 1 Tbps), coupling loss (e.g., < 0.5 dB/fiber connection) and estimated mean time between failures (MTBF) under standard military environmental conditions (e.g., MIL-STD-810H). Prepare a
- Outcome: A comprehensive Phase II development plan that identifies the PIC foundry and packaging facility, including preliminary packaging designs and a proof-of-concept simulation report.
Phase II
Develop, fabricate, and demonstrate a working CPO prototype based on the Phase I design. Ensure that the
- Deliverables: The prototype shows compatibility with a notional sensor ROIC (i.e., greater than or equal to 640 x 480 Video Graphics Array (VGA) format and less than or equal to 10 um pitch). (Note: The ROIC digital signals can be emulated using a pseudo-random number generator (PRNG).) Demonstrate that the prototype is capable of cryocooled operation with full transceiver functionality, i.e., efficient electrical-optical conversion and transmission from cold space, data transfer through optical fiber, and optical-electrical conversion in warm space.
- Testing: Conduct laboratory testing in a relevant cryogenic environment (70-140K) to validate bandwidth, power/energy efficiency, coupling loss, and bit-error-rate (BER) for the entire transceiver operation. Perform preliminary environmental testing (thermal cycling, vibration) to prove the viability of the optical attachment and packaging under stress.
- Outcome: Deliver the prototype device, test reports, and a Phase III transition plan for integrating the technology into a specific DON system or sensor suite.
Phase III Dual Use Applications
Transition to Navy maritime sensing program of record and commercial sensing applications.
- DON/DoW Application: Transition the ruggedized CPO technology to military Prime Contractors for integration into maritime Infrared Search and Track (IRST) and airborne Intelligence, Surveillance, and Reconnaissance (ISR) platforms, and mobile command centers requiring high-performance computing (HPC) at the edge.
- Commercial Application: Transition the technology to commercial markets, specifically targeting telecom infrastructure, hyperscale data centers, and Super Intelligence/Machine Learning (SI/ML) compute clusters where thermal efficiency and bandwidth density are highly valued.
References
Yi, Y. and Yu, B. "3D Optoelectronics and Co-Packaged Optics: Innovations, Challenges, and Future Trends." IEEE Journal of Selected Topics in Quantum Electronics, vol. 32, no. 2: 3-D Horizons in Photonics: Integrated Circuits, March-April 2026, Art no. 3700515, pp. 1-15. https://doi.org/10.1109/JSTQE.2025.3641790
Estrella, S. B. et al. "Cryogenic optical interconnects for infrared sensing applications." 2022 IEEE Research and Applications of Photonics in Defense Conference (RAPID), 2022. https://doi.org/10.1109/RAPID56086.2022.9911270
Chen, G.; Wang, G.; Wang, Z. and Wang, L. “Electronic Chip Package and Co-Packaged Optics (CPO) Technology for Modern AI Era: A Review.” Micromachines 2025, 16, 431. https://doi.org/10.3390/mi16040431
Tian, W.; Hou, H.; Dang, H; Cao, X.; Li, D.; Chen, S. and Ma, B. “Progress in Research on Co-Packaged Optics.” Micromachines 2024, 15, 1211. https://doi.org/10.3390/mi15101211
Keywords
Co-packaged optics; CPO; silicon photonics; interconnects; read out integrated circuit; ROIC; sensors; Electro-Optical/Infrared; EO/IR
Frequently asked questions
What is DON27TZ02-NV001?
It is a Department of the Navy STTR topic to develop co-packaged optics architectures and integration techniques for cryocooled EO/IR sensors that reduce electrical wirebonds, increase bandwidth density, and survive rugged maritime environments.
When is DON27TZ02-NV001 due?
Proposals are due January 6, 2027, 12:00 PM ET. DSIP pre-release began November 4, 2026, and direct contact with the topic authors is allowed only until the topic opens on December 2, 2026, 8:00 AM ET. After that, questions go through DSIP Topic Q&A.
Is this a Phase I or Direct-to-Phase II topic?
It is a Phase I STTR topic. Phase I is a feasibility study with architectural, signal integrity, and thermal/mechanical modeling. Phase II fabricates and tests a working prototype. As an STTR, it requires a research-institution partner.
Do I need a real sensor ROIC for the Phase II demonstration?
No. The prototype must show compatibility with a notional ROIC of at least 640 x 480 format and 10 um pitch or finer, and the topic states that the ROIC digital signals can be emulated using a pseudo-random number generator.