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Topic DON27BZ02-NV011 from the DoW SBIR 2027 BAA, Release 2. Pre-release now; proposals due January 6, 2027, 12:00 PM ET.
Quick answer
DON27BZ02-NV011 is a Department of the Navy SBIR topic seeking a wafer-scale 3D heterogeneous integration process that directly bonds III-V MWIR detector wafers to silicon ROIC wafers, replacing die-level indium bump-bonding. It follows a standard Phase I then Phase II path. Proposals are due January 6, 2027, 12:00 PM ET.
Solicitation at a glance
- Topic number: DON27BZ02-NV011
- Official title: Low-cost Mid-wave Infrared Focal-Plane Array (FPA) Fabrication through Direct-bond Interconnection
- Agency: Department of the Navy
- Program: SBIR (DoW SBIR 2027 BAA, Release 2)
- Award type: Phase I (see topic text for Phase II)
- Award amount: Phase I base up to $200,000 plus an option up to $115,000. Source: Navy Release 2 instructions in DSIP.
- CMMC level: Level 2 (Self)
- ITAR: Yes. Export-controlled (ITAR/EAR); see topic text
- Technology areas: None
- Pre-release (direct TPOC contact allowed): November 4 to December 2, 2026, 8:00 AM ET
- Opens in DSIP: December 2, 2026, 8:00 AM ET
- Proposals due: January 6, 2027, 12:00 PM ET
- Official source: DSIP Topics app (search DON27BZ02-NV011)
BW&CO's take
What the Department of the Navy wants
MWIR focal-plane arrays use III-V detector materials that are not CMOS compatible, so today they are assembled by flip-chip bonding detector and ROIC die through dense arrays of indium bumps, a labor-intensive, low-yield, costly process. The Navy wants direct-bond interconnection (DBI) or a similar process that bonds a III-V MWIR detector epi-layer wafer to a Si-ROIC wafer at wafer scale. Required specs are pixels of 10 um or smaller, at least 2K x 2K format, and coverage of at least 3-5 um. Phase I plans the process, characterization, and a per-FPA cost comparison against bump-bonding. Phase II fabricates multiple wafers of FPAs, then dices and characterizes them.
Who is a good fit
- Hands-on wafer-to-wafer hybrid bonding or DBI process experience, ideally with heterogeneous materials
- III-V MWIR detector epi-layer growth or processing, including substrate removal
- Access to a foundry and to a commercially available Si ROIC that supports 10 um or smaller pixels at 2K x 2K or larger format
- FPA characterization capability for inter-wafer voids, pixel operability, and yield, plus the ability to build a credible cost model versus bump-bonding
Watch-outs
- The topic is ITAR-restricted. Plan for export-control compliance, including limits on foreign national participation.
- The format and pixel requirements are firm: pixel size of 10 um or less and at least 2K x 2K format, with detector response covering at least 3-5 um. Proposals that scale down these targets risk being noncompliant.
- Phase II requires fabricating multiple wafers of FPAs, so the proposal needs a believable foundry and process access plan, not only a bonding concept.
- The topic requires CMMC Level 2 (Self).
Think your company fits DON27BZ02-NV011? Talk with BW&CO before the January 6 deadline.
Plan Your DON27BZ02-NV011 Submission
Official topic text (verbatim from DSIP)
The text in this section is copied word for word from the official DSIP topic as published on November 4, 2026. DSIP is the official source and topics can be amended. Always confirm the current version at dodsbirsttr.mil before you submit. Our commentary above is BW&CO's interpretation, not Government guidance.
Title
Low-cost Mid-wave Infrared Focal-Plane Array (FPA) Fabrication through Direct-bond Interconnection
Objective
Develop a focal-plane array (FPA) fabrication process based on wafer-scale 3D-heterogeneous integration that enables a mid-wave infrared (MWIR) III-V detector epi-layer wafer to be directly bonded to a Silicon-based read-out integrated circuit (Si-ROIC) wafer, thereby eliminating the inefficient die-level Indium (In) bump-bonding process currently required to assemble Mid-wave Infrared (MWIR) FPA sensor chips.
Description
Electro-Optic and Infrared (EO/IR) sensors are used in a wide variety of applications, such as navigation, wide-area surveillance, and targeting. Operating in the visible and near-IR bands, EO sensors are available with small pixels and in large arrays at low cost, because the Si-detector wafer and Si-ROIC wafer can be 3D-integrated directly through wafer-to-wafer bonding with high yield at high volume based on material and complementary metal-oxide-semiconductor (CMOS)-process compatibility. By contrast, sensors operating in the MWIR employ III-V detector materials, which are not CMOS-process compatible, while III-V epi-layer detectors cannot be epitaxially grown directly on Si, as required to produce the crystalline order of high-quality detectors [Refs 1-2]. Instead, the III-V detector epi-layer is grown on a lattice-compatible substrate wafer, which is then flip-chip bonded to a Si-ROIC through a dense array of sub-pixel indium bumps placed on each wafer, followed by detector-substrate removal. The technically demanding process of depositing, aligning, and compressing the dense arrays of indium bumps on detector and ROIC die, results in a labor-intensive, inefficient, low-yield process for IR FPA fabrication, which greatly increases cost.
In recent years, 3D-heterogeneous integration has enabled a single integrated chip of greater overall functionality to be realized at reduced cost by assembling multiple smaller chips, each having unique functionality, material, node size, and/or foundry origin. Direct-bond interconnection (DBI) [Refs 3-5] is a 3D-heterogeneous integration technique that can potentially enable low-cost MWIR FPA fabrication. In principle, DBI should enable very large format FPAs with small pixels to be fabricated, as the process is largely independent of wafer and pixel size, in contrast to conventional bump-bonding. Moreover, the DBI process utilizes a temperature range that is compatible with MWIR IR detector materials.
The goal of this SBIR topic is to demonstrate the use of DBI or a similar process for fabrication of high-performance, large format, small-pixel, MWIR FPAs at low cost with the objective of refining the technique sufficiently to potentially replace conventional bump-bonding.
Phase I
Plan a detailed concept for a FPA fabrication and characterization process, including a risk assessment. While the pixel unit cell design is flexible, a pixel size of less than or equal to 10 micro-meters (um) and format of at least 2K x 2K are required, but otherwise any existing or commercially available Si-based ROIC can potentially be used for this effort. The III-V detector epi-layer spectral response must cover at least the MWIR band (3-5 um). The specific foundry and fabrication process steps will be determined in Phase I. Develop a detailed FPA characterization plan, including measurement of inter-wafer voids, pixel operability, and yield. Perform a per-FPA cost analysis that compares DBI or the selected alternative process to conventional bump-bonding and includes an assessment of the cost impact of process selection trade-offs.
Phase II
Use the DBI or selected alternative process to fabricate multiple wafers of FPAs having less or equal to 10 um pixels and greater than or equal to 2K x 2K format. Dice and thoroughly characterize the FPAs. Integrate one or more FPA sensor chips into an imaging system and subsequent optical performance characterization (favorable but is not required under this effort.) Prepare a Phase III commercialization/transition plan.
Phase III Dual Use Applications
Build and test an imaging sensor employing a DBI-fabricated FPA with available Phase III funding upon successful completion of Phase II.
The advancement of MWIR imagers could support many dual-use applications, such as border security, law enforcement, and industrial process monitoring. In general, the advancement of 3D-HI and DBI specifically could facilitate the development of novel micro-electronic devices beyond MWIR imagers.
References
Rogalski, A. "Recent progress in infrared detector technologies." Infrared Physics & Technology, 54(3), 2011, pp. 136-154. https://www.scirp.org/reference/referencepapers?referenceid=838480
Martyniuk, P. and Rogalski, A. "HOT infrared photodetectors." Opto-Electronics Review, 21(2), 2013, pp. 239-257. https://www.researchgate.net/publication/257909096_HOT_infrared_photodetectors
US Patent 9,082,627: Method for low temperature bonding and bonded structure (covers the core process of room or low-temperature dielectric-to-dielectric and metal-to-metal bonding). https://patents.google.com/patent/US9082627B2/zh
US Patent 6,962,835: Method for room temperature metal direct bonding. https://patents.google.com/patent/US6962835B2
US Patent 9,391,143: Method for low temperature bonding and bonded structure. https://patents.google.com/patent/US9391143B2
Keywords
Focal plane array, FPA, direct-bond interconnection, DBI, 3D heterogeneous integration, 3D HI, infrared imaging, IR, semiconductor processing, read out integrated circuit, ROIC, sensor chip assembly, SCA, mid-wave infrared, MWIR, IR detector materials
Frequently asked questions
What is DON27BZ02-NV011?
It is a Department of the Navy SBIR topic to develop a wafer-scale 3D heterogeneous integration process, such as direct-bond interconnection, that bonds a III-V MWIR detector wafer directly to a silicon ROIC wafer and eliminates die-level indium bump-bonding for MWIR focal-plane arrays.
When is DON27BZ02-NV011 due?
Proposals are due January 6, 2027, 12:00 PM ET. DSIP pre-release began November 4, 2026, and direct contact with the topic authors is allowed only until the topic opens on December 2, 2026, 8:00 AM ET. After that, questions go through DSIP Topic Q&A.
Is this a Phase I or Direct-to-Phase II topic?
It is a standard Phase I topic. Phase I plans the fabrication and characterization process, assesses risk, and compares per-FPA cost against bump-bonding. Phase II fabricates, dices, and characterizes multiple wafers of FPAs.
Can I use an existing ROIC, or must I design one?
The pixel unit cell design is flexible and any existing or commercially available Si-based ROIC can potentially be used, as long as the result meets 10 um or smaller pixels and at least 2K x 2K format. The specific foundry and process steps are determined in Phase I.