OSW Basic Research STTR OSW26TZ06-NV005: Ultrafast Nonvolatile Memory Based on Sliding Ferroelectricity in Moire Polar Homostructures
Quick Answer
OSW26TZ06-NV005 is a Phase I STTR topic under the Office of the Secretary of War, Basic Research, 2026 STTR Broad Agency Announcement, Release 6. The program exists to move discoveries out of university laboratories and into small businesses, and this topic is a direct descendant of Department of War Multidisciplinary University Research Initiative investments. The ask is a nonvolatile memory built on sliding ferroelectricity in twisted van der Waals stacks. The award must not exceed $250,000 over 12 months, and the technical volume is capped at 15 pages. The topic opens September 23, 2026 and closes October 21, 2026 through the Defense SBIR/STTR Innovation Portal.
The physics is specific and recent. Twisted stacks of van der Waals crystals can form moire superlattices with polar domains whose dipoles are antiferroelectrically aligned and controllable by applied electric fields. Sliding ferroelectricity arises from nanometer-scale interlayer sliding, coupling in-plane atomic displacement to out-of-plane polarization switching. The mechanism has been demonstrated in bilayer hexagonal boron nitride and in semiconducting transition metal dichalcogenides, where polarization reversal can occur with minimal energy dissipation.
The topic is candid about what it takes to compete. Advancement and prototype development requires combined multidisciplinary expertise in the design, fabrication, measurement, and modeling of lattice dynamics in twisted moire van der Waals structures, as well as charge transport and optoelectronics in van der Waals materials. That is four distinct competencies, and no single-discipline team has them.
Phase I is unusual in one respect worth noting early: it asks you to establish the performance targets rather than hit them. During Phase I, measurable indicators will be quantified to establish appropriate performance targets for Phases II and III and to enable benchmarking against existing nonvolatile memory technologies.
Topic At a Glance
Topic number: OSW26TZ06-NV005
Title: Development of Ultrafast Nonvolatile Memory Based on Sliding Ferroelectricity in Moire Polar Homostructures
Agency: Office of the Secretary of War, Basic Research, administered by the OUSW(R&E) Science and Technology Foundations STTR Program
Solicitation: OSW Basic Research 2026 Small Business Technology Transfer Broad Agency Announcement, Release 6, Proposal Submission Instructions
Program type: Phase I
Award: must not exceed $250,000
Period of performance: 12 months
Technical volume: not to exceed 15 pages. Technical volumes exceeding 15 pages will be deemed non-compliant and will not be evaluated
Component Technology Priority Areas: Advanced Materials, Microelectronics, Quantum Science
OUSW (R&E) Critical Technology Area: Quantum and Battlefield Information Dominance
Projected CMMC level requirement: Level 1
Export control status: no topic-level ITAR or EAR restriction paragraph appears on this topic, and none appears on any of the seven topics in this release
Classification: Phase I and Phase II efforts are expected to be performed at the Unclassified level
Material systems named: bilayer hexagonal boron nitride and semiconducting transition metal dichalcogenides
Readout platforms named: graphene field-effect transistors and transition-metal-dichalcogenide-based field-effect transistors
Performance indicators to quantify in Phase I: switching speed, switching energy, endurance, retention, readout fidelity, device-to-device reproducibility, and scalability beyond single-device demonstrations
Prior investment: Department of War Multidisciplinary University Research Initiative funding has already demonstrated twisted two-dimensional heterostructures advanced into atomically thin twistronic memory cell prototypes
Research institution partner: required, as with all STTR awards, along with a written allocation of rights agreement if selected
Phase II structure: a 10 to 12 month base period not to exceed $1,000,000 plus a 10 to 12 month option period not to exceed $1,000,000, with the entire Phase II effort not exceeding $2,000,000
Technical and Business Assistance: Phase I up to $6,500, Phase II up to $50,000 per project, in addition to the cost ceilings and not subject to profit or fee, using the mandatory SBIR/STTR TABA Request Form in Volume 5
Percentage of Work: deviations from the POW requirements are not permitted
Company Commercialization Report: information contained in the CCR will not be considered by S&T Foundations during proposal evaluations
Topic open date: September 23, 2026
Proposal deadline: October 21, 2026
Submission portal: DSIP at dodsbirsttr.mil
Keywords: sliding ferroelectricity, moire superlattice, van der Waals materials, nonvolatile memory, twistronics, two-dimensional materials, ferroelectric domains, graphene field-effect transistor, transition metal dichalcogenides, low-power memory, high-endurance memory, polar homostructures
What the Program Is For, Which Shapes How You Write
The S&T Foundations STTR Program has a purpose distinct from most SBIR and STTR programs, and it is stated plainly.
The program aims to facilitate the transition of basic research to applied research by collaborations between academic researchers and small businesses, as well as stimulating technological innovation, strengthening the role of small business in meeting DoW research and development needs, fostering and encouraging participation by minority and disadvantaged persons in technological innovation, and increasing the commercial application of DoW-supported research or research and development results.
The program focuses on exploiting scientific discoveries from the DoW basic research programs and providing a mechanism to further scientific development, maturation, and commercialization. High-risk with potential for high-reward approaches are sought in addressing the scientific challenges described in the topics. These approaches should be stimulated by early research in academia supported by DoW basic research programs.
The consequence for your technical volume
In addition to the Phase I proposal content specified in the DoW STTR BAA, this program requires a narrative description of how early research in academic labs will be transitioned to the small business via this opportunity.
The Phase I Technical Proposal must also include a preliminary Phase II Plan specifying the overall vision, approach, and potential product proposed at the end of Phase II.
Both must be included within the 15-page limit.
So the technical volume carries three things a standard Phase I proposal would not: the transition narrative, the preliminary Phase II Plan, and the usual Phase I technical content, all in fifteen pages. Plan the page budget before you draft.
What the Topic Is Actually Asking For
The objective
Develop ultrafast, high-endurance, nonvolatile memory technology based on sliding ferroelectricity in polar moire van der Waals homostructures.
Note the word homostructures. A homostructure is the same material twisted against itself, as opposed to a heterostructure stacking different materials. That distinction is in the title and the objective, and it matters: twisted bilayer hexagonal boron nitride is a homostructure, and the moire polarity arises from the twist rather than from a chemical interface.
The mechanism
Twisted stacks of van der Waals crystals can form moire superlattices with polar domains whose dipoles are antiferroelectrically aligned and controllable by applied electric fields.
Sliding ferroelectricity arises from nanometer-scale interlayer sliding in van der Waals materials, coupling in-plane atomic displacement to out-of-plane polarization switching.
This mechanism has been demonstrated in bilayer hexagonal boron nitride and semiconducting transition metal dichalcogenides, where polarization reversal can occur with minimal energy dissipation.
That last clause is the whole value proposition. Conventional ferroelectric switching moves ions through a lattice against substantial barriers. Sliding ferroelectricity moves one atomic plane laterally against a van der Waals gap, which is a far weaker restoring force. Minimal energy dissipation per switch, and no chemical bond breaking, is what should give both the speed and the endurance the title promises.
Why the Department is funding this now
Recent Department of War investments through the Multidisciplinary University Research Initiative have demonstrated advances in twisted two-dimensional heterostructures into atomically thin twistronic memory cell prototypes with potential advantages in speed, endurance, energy efficiency, and scalability.
That sentence is your transition narrative handed to you. This is MURI-derived science, the program exists to move MURI-derived science into small businesses, and the topic says the prototypes already exist. Identify which MURI, which university group, and which people, and the required narrative on transitioning early academic research writes itself.
The four required competencies
The advancement and prototype development requires a combined multidisciplinary expertise in the design, fabrication, measurement, and modeling of lattice dynamics in twisted moire van der Waals structures, as well as charge transport and optoelectronics in van der Waals materials.
Read that as a staffing requirement. Design and fabrication of twisted stacks, which is a specialized and largely manual craft. Measurement, including the electrical and optical characterization of nanoscale polar domains. Modeling of lattice dynamics, which is where the sliding physics lives. And charge transport and optoelectronics in van der Waals materials, which is what makes a readout work.
Since qualifications of key personnel is the second-ranked evaluation criterion, mapping named people onto these four competencies is one of the highest-value things you can do with your fifteen pages.
The technical approach the topic wants
The technical approach should exploit the atomically thin nature, low defect density, and strong in-plane bonding of van der Waals materials to develop sliding ferroelectric nonvolatile memory devices designed to outperform current memory technologies in speed, endurance, and scalability.
Engineered nanoscale polar domains in moire superlattices will serve as nonvolatile memory cells based on local ferroelectricity.
To demonstrate the electrical and optical readouts in the designed nonvolatile memory devices, the proposal should leverage the scalability and controllability features of well-established systems, such as graphene field-effect transistors and transition-metal-dichalcogenide-based field-effect transistors.
Three material properties are named as the levers: atomically thin nature, low defect density, and strong in-plane bonding. Each maps to a memory metric. Atomically thin gives you scaling density. Low defect density gives you endurance and reproducibility. Strong in-plane bonding is what lets a layer slide laterally without the lattice degrading, which is the fatigue-resistance argument.
And note the readout instruction. You are not asked to invent a readout. You are told to use graphene or TMD field-effect transistors because they are well established and scalable. Following that instruction is cheaper and more credible than proposing something novel on the readout side, and it lets your novelty stay concentrated in the memory cell.
Phase I Requirements
Demonstrate the feasibility of optimal moire superlattice design for fast and durable sliding ferroelectric domain reversal, including domain wall pinning strategies and nanostructured polar moire superlattice fabrication.
Evaluate and analyze electrical and optical readout schemes using graphene field-effect transistors or transition-metal-dichalcogenide-based devices integrated with moire polar domain structures.
Perform quantitative analysis of the switching behavior, retention, readout fidelity, speed, energy efficiency, and endurance indicators under optimal device operating conditions.
The success of the project will be evaluated using measurable performance indicators, including switching speed, switching energy, endurance, retention, readout fidelity, device-to-device reproducibility, and scalability beyond single-device demonstrations. During Phase I, these values will be quantified to establish appropriate performance targets for Phases II and III and to enable benchmarking against existing nonvolatile memory technologies.
Reading this scope carefully
Three tasks and one measurement framework. The tasks are superlattice design including domain wall pinning, readout scheme evaluation on established FET platforms, and quantitative characterization.
The measurement framework is the part worth dwelling on, because it is unusual. Seven indicators are named, and Phase I quantifies them in order to establish the targets for Phases II and III. You are not being asked to beat a specification. You are being asked to produce the specification, honestly, and to benchmark it against existing nonvolatile memory.
That is an invitation to be rigorous rather than optimistic, and it changes how you should write. A proposal that promises specific Phase II numbers it cannot yet justify is answering a different question. A proposal that lays out exactly how each of the seven indicators will be measured, with what instruments, on what device geometry, and how the results will be compared against flash, magnetoresistive RAM, resistive RAM, and conventional ferroelectric FETs, is answering this one.
Domain wall pinning, which is the technical crux
Domain wall pinning strategies appear in the Phase I task list and again in Phase II, where the topic says particular attention must be paid to the atomic-scale configuration of the engineered sliding ferroelectric state and the role of domain-wall pinning for controllability.
That repetition is a signal. In a moire superlattice, the polar domains are defined by the twist, and the domain walls between them are where switching happens. If the walls move freely, the state is not stable and retention fails. If they are pinned too strongly, switching costs energy and speed, and the endurance advantage evaporates. The engineering problem is controlled pinning: enough to hold a state, little enough to switch cheaply.
A proposal with a specific, physically grounded pinning strategy, whether through nanostructured local gates, deliberate defect placement, strain engineering, or twist-angle gradients, is addressing the thing the topic names twice.
Phase II and Phase III, For Planning Purposes
Phase II
Develop integrated sliding-ferroelectric memory-device prototypes and array-level architectures for more practical use, focusing on systematic evaluation of memory operation benchmarks including endurance, switching speed, and energy efficiency under realistic operating conditions.
Particular attention must be paid to address the atomic-scale configuration of the engineered sliding ferroelectric state and the role of domain-wall pinning for controllability.
Address scaling and manufacturability beyond single-device demonstrations, aiming at initial demonstration of wafer-scale patterning of local gates, partitioning of van der Waals structures into individual memory cells, and device packaging of memory arrays.
Finally, establish quantitative comparison against competing nonvolatile memory technologies by evaluating switching energy, achievable integration density, and intrinsic fatigue resistance for long-term device operation.
The move from single devices to arrays is the hard part, and the topic names the three specific manufacturing problems: wafer-scale patterning of local gates, partitioning van der Waals structures into individual cells, and packaging. Twisted van der Waals stacks are famously made one at a time by hand, so a credible answer to wafer-scale anything is a substantial differentiator. Address it in the preliminary Phase II Plan even though it is not a Phase I task.
Phase III
Develop a high-speed memory device with low-power device operation, emphasizing energy-efficient memory for edge computing, high-density embedded memory, and robust architectures for defense-relevant electronics.
Identify use cases where atomically thin, rapid, durable and low power switching will provide a demonstrable advantage over existing technology, and describe approaches to industrial adoption and system level integration. Relatively low-power and moderate-speed operation offered by the developed technology can provide added value to general purpose edge-computing applications.
As performance metrics are established during Phases I and II, broader applications will be evaluated, including high-density embedded memory, neuromorphic and in-memory computing, reconfigurable logic, radiation-tolerant electronics, cryogenic control electronics, and memory components integrated with two-dimensional semiconductor platforms.
Note the phrase "relatively low-power and moderate-speed operation." That is a notably honest hedge against the title's promise of ultrafast, and it tells you the government will accept a device that wins on energy rather than raw speed. Six broader applications are listed, and two of them, radiation-tolerant electronics and cryogenic control electronics, are defense-specific niches where an atomically thin ferroelectric could be genuinely differentiated rather than competing head-on with commercial memory.
The STTR Partnership and Allocation of Rights
This is an STTR, so a formal partnership with a research institution is a condition of the award rather than a feature of your approach.
If a small business concern is selected for an STTR award, they must negotiate a written agreement between the small business and their selected research institution that allocates intellectual property rights and rights to carry out follow-on research, development, or commercialization. The instructions point to the Model Agreement for the Allocation of Rights.
STTR awards also carry statutory minimum work shares: the small business must perform at least 40 percent of the work and the single partnering research institution at least 30 percent. The OSW Basic Research instructions direct proposers to follow all general instructions in the DoW STTR Program solicitation, which is where those requirements live. Read that document, not only this one.
What the split looks like on this topic
The natural division follows the four named competencies. The research institution owns the twisted stack design and fabrication, the lattice dynamics modeling, and the nanoscale characterization of polar domains, since that is where twistronics expertise and the requisite instrumentation live. The small business owns the device integration onto graphene or TMD field-effect transistors, the electrical and optical readout engineering, the quantitative benchmarking against commercial memory, and the path toward wafer-scale processing.
Because this topic descends directly from Multidisciplinary University Research Initiative work, the institution's contribution is substantive rather than nominal, which makes a 30 percent share easy to justify. Name the institution, the faculty principal investigator, the specific instruments, and the tasks.
Note that the program instructions ask you to plan carefully for research involving animal or human subjects, biological agents, and similar elements, and warn that the short duration of a Phase I effort may preclude such plans unless coordinated before a contract is awarded.
The Phase II Submission Window, Which You Must Plan For Now
This program mechanic catches first-time applicants and it deserves its own section.
Phase II proposals may only be submitted by Phase I awardees. All Phase I awardees are eligible to submit a Phase II proposal. Phase II selections are based, in large part, on the success of the Phase I effort, so it is vital for small business concerns to discuss the Phase I project results with their Technical Point of Contact.
The 30-day window to submit a Phase II proposal is expected to commence 6 to 9 months into the Phase I period. The details on the due date, content, and submission requirements will be provided to Phase I awardees by the S&T Foundations STTR Program Management Office via subsequent notification.
This will be the only opportunity to submit a Phase II proposal for the Basic Research topics. The S&T Foundations STTR Program cannot accept proposals outside the established Phase II submission dates, and proposals received at any other time will not be evaluated.
Phase II proposals are expected to be structured as a 10 to 12 month base period not to exceed $1,000,000 plus a 10 to 12 month option period not to exceed $1,000,000, with the entire Phase II effort not exceeding $2,000,000.
Why this changes your Phase I plan
The Phase II window opens 6 to 9 months into a 12-month Phase I. You will be writing your Phase II proposal while the Phase I effort is still running, arguing Phase II merit on partial results.
Structure the Phase I schedule so your most persuasive results land in the first six months, and say in your Phase I plan what will be complete by then. Establish the Technical Point of Contact relationship early in performance, because the program says discussing Phase I results with the TPOC is vital and the missed window is unrecoverable.
Funding, Cost Structure, and Program Mechanics
The award
The Phase I amount must not exceed $250,000 over a period of 12 months. The Government anticipates making multiple Phase I awards under this topic, subject to the availability of funds and the receipt of meritorious proposals.
Note also that due to limited funding, S&T Foundations reserves the right to limit awards under any topic.
The 15-page limit is a hard compliance gate
The technical volume is not to exceed 15 pages and must follow the formatting requirements provided in the DoW STTR Program BAA. Technical volumes exceeding 15 pages will be deemed non-compliant and will not be evaluated.
Note the phrasing. Not "pages in excess will not be considered," which is what several other components say. Non-compliant and not evaluated. An over-length technical volume loses the whole proposal, not the extra pages. Count the pages before you submit, and remember that the transition narrative and the preliminary Phase II Plan both sit inside the limit.
Percentage of Work
Review the updated Percentage of Work calculation details included in the DoW Program BAA. Deviations from the POW requirements are not permitted.
With a research institution performing at least 30 percent of the work, your POW arithmetic needs to be right before you finalize the subaward. Model it first.
Technical and Business Assistance
Phase I awardees may request up to $6,500 in TABA funding. Phase II awardees may request up to $50,000 per Phase II project. TABA funding is in addition to the Phase I and Phase II cost ceilings and is not subject to profit or fee.
All requests for TABA must be completed using the SBIR/STTR TABA Request Form, and the completed form must be included in Volume 5 of the proposal submission in DSIP. OSW will not accept requests for TABA that do not utilize the form or that are not included as a submission document in Volume 5.
The form requirement is absolute. For this topic, intellectual property counsel is the standout use, because twisted van der Waals device architectures emerging from MURI-funded university work carry real IP complexity, and a required allocation of rights agreement makes getting the structure right early valuable. Semiconductor manufacturing and foundry transition consulting is a close second, given the wafer-scale patterning challenge in Phase II.
The Company Commercialization Report is not evaluated
Completion of the CCR as Volume 4 is required, but information contained in the CCR will not be considered by S&T Foundations during proposal evaluations. Complete it because it is required, and put your commercialization effort into the technical volume instead, where it is scored.
Evaluation criteria, in stated order of importance
This is one of the most useful things in the OSW Basic Research instructions.
All proposals will be evaluated in accordance with the evaluation criteria listed in the DoW solicitation. The criteria will be in descending order of importance with technical merit, soundness, and innovation of the proposed approach being the most important, followed by qualifications of key personnel, and then followed by commercialization potential.
Evaluation of the Phase I proposal will include an assessment of not only the feasibility studies planned for Phase I but the overall approach and product proposed at the end of Phase II.
Awards will be made on the basis of technical evaluations using the criteria described in the DoW Solicitation and availability of S&T Foundations STTR funds.
Three things follow. Technical merit dominates, so that is where your pages belong. Key personnel ranks second, ahead of commercialization, which means naming the right people matters more than the market analysis. And the preliminary Phase II Plan is not a formality, because the evaluation explicitly assesses the overall approach and product proposed at the end of Phase II.
Only Government personnel will evaluate proposals, with the exception of personnel from Strategic Analysis, Inc who provide programmatic and administrative assistance for all topics.
Notification and debriefings
Proposing firms will be notified of selection or non-selection status for a Phase I award within 90 days of the closing date of the topic. Notifications will be issued through DSIP to both the firm's Corporate Official and Principal Investigator of record. Ninety days from October 21, 2026 is approximately January 19, 2027.
Non-selected proposers may request a written debriefing within 30 calendar days of the select or non-select notification, as specified in that notification. Debriefs are typically provided in writing via email to the Corporate Official identified in the firm proposal within 30 days of receipt of the request. Requests for oral debriefs may not be accommodated. If contact information for the Corporate Official has changed since proposal submission, a notice of the change on company letterhead signed by the Corporate Official must accompany the debrief request.
The debriefing provision is genuinely valuable and underused. If you are not selected, a written debrief tells you what to fix, and this program recurs.
Refer to the DoW solicitation for procedures to protest the announcement. As prescribed in FAR 33.106(b) and FAR 52.233-3, protests after award should be submitted to osd.ncr.ousd-r-e.mbx.sbir-sttr-protest@mail.mil.
Foreign nationals, privacy, and classification
If the offeror proposes to employ a foreign national, refer to the DoW Solicitation for definitions and reporting requirements. Ensure no Privacy Act information is included in the submittal.
Phase I and Phase II efforts are expected to be performed at the Unclassified level.
The unclassified expectation matters, because university research groups are typically open-research environments with international students and postdocs. This program is compatible with that, unlike several other components in this cycle, and no topic-level ITAR restriction appears anywhere in this release. Follow the DoW Solicitation reporting requirements for any foreign nationals you propose.
Questions
Specific questions pertaining to the administration of the STTR Program and these proposal preparation instructions should be directed to Jason Day at jason.o.day.civ@mail.mil.
The instructions do not state that DSIP Topic Q&A is unavailable, so the standard DoW STTR Program BAA process applies and Topic Q&A closes to new questions two weeks before the topic closes, on October 7, 2026.
The References
Three, and they are the primary literature of this field rather than reviews. Read all three.
Yasuda, Wang, Watanabe, Taniguchi, and Jarillo-Herrero, Science 372, 1458 to 1462, 2021. This is the stacking-order ferroelectricity result in twisted boron nitride and the foundation of the field.
Ko, Yuk, Engelke, Carr, Kim, Park, Heo, Kim, Kim, Kim, Taniguchi, Watanabe, Park, Kaxiras, Yang, Kim, and Yoo, Nature Materials 22, 992 to 998, 2023. The twenty-author list is itself informative: this is the multidisciplinary collaboration the topic describes when it says advancement requires combined expertise across design, fabrication, measurement, and modeling.
Yasuda, Zalys-Geller, Wang, Bennett, Cheema, Watanabe, Taniguchi, Kaxiras, Jarillo-Herrero, and Ashoori, Science 385, 53 to 56, 2024. The most recent of the three and the closest to a memory device demonstration.
The pattern is worth noticing. Three high-impact papers from 2021, 2023, and 2024, with substantial author overlap, from the groups the Department has been funding. If your research institution partner is one of those groups, say so plainly. If it is not, you need a clear account of why your team can compete with them, because a reviewer will be comparing you to the authors of these papers.
Bring your own literature on the memory engineering side. The topic gives you no citations for endurance testing methodology, array architecture, or benchmarking against commercial nonvolatile memory, and the DoW STTR Phase I content requirements expect you to demonstrate awareness of the state of the art.
Timeline and What to Do When
The dates
Topic opens: September 23, 2026
DSIP Topic Q&A closes: October 7, 2026, two weeks before the topic closes, per the DoW STTR Program BAA
Proposal deadline: October 21, 2026
Selection notification: within 90 days of the closing date, approximately January 19, 2027, through DSIP to both the Corporate Official and the Principal Investigator of record
Debriefing request window: within 30 calendar days of notification
Period of performance: 12 months
Phase II submission window: a 30-day window expected to commence 6 to 9 months into the Phase I period, and the only opportunity
Frequently Asked Questions
What is OSW Basic Research STTR topic OSW26TZ06-NV005?
OSW26TZ06-NV005 is a Phase I STTR topic titled "Development of Ultrafast Nonvolatile Memory Based on Sliding Ferroelectricity in Moire Polar Homostructures," released under the OSW Basic Research 2026 STTR Broad Agency Announcement, Release 6. The objective is to develop ultrafast, high-endurance, nonvolatile memory technology based on sliding ferroelectricity in polar moire van der Waals homostructures.
What is sliding ferroelectricity?
Sliding ferroelectricity arises from nanometer-scale interlayer sliding in van der Waals materials, coupling in-plane atomic displacement to out-of-plane polarization switching. Twisted stacks of van der Waals crystals form moire superlattices with polar domains whose dipoles are antiferroelectrically aligned and controllable by applied electric fields. The topic notes that polarization reversal can occur with minimal energy dissipation, which is the core value proposition.
Which materials has this been demonstrated in?
The topic states the mechanism has been demonstrated in bilayer hexagonal boron nitride and semiconducting transition metal dichalcogenides.
What expertise does the topic say I need?
Combined multidisciplinary expertise in the design, fabrication, measurement, and modeling of lattice dynamics in twisted moire van der Waals structures, as well as charge transport and optoelectronics in van der Waals materials. That is four competencies, and since key personnel is the second-ranked evaluation criterion, mapping named people onto all four matters.
What does Phase I have to accomplish?
Demonstrate feasibility of optimal moire superlattice design for fast and durable sliding ferroelectric domain reversal, including domain wall pinning strategies and nanostructured polar moire superlattice fabrication. Evaluate and analyze electrical and optical readout schemes using graphene or TMD field-effect transistors integrated with moire polar domain structures. And perform quantitative analysis of switching behavior, retention, readout fidelity, speed, energy efficiency, and endurance indicators under optimal device operating conditions.
What performance targets must I hit in Phase I?
None are specified, and that is deliberate. Seven measurable indicators are named, switching speed, switching energy, endurance, retention, readout fidelity, device-to-device reproducibility, and scalability beyond single-device demonstrations, and Phase I quantifies these values to establish appropriate performance targets for Phases II and III and to enable benchmarking against existing nonvolatile memory technologies. You are producing the specification, not meeting one.
What readout should I use?
The topic instructs proposers to leverage the scalability and controllability features of well-established systems such as graphene field-effect transistors and transition-metal-dichalcogenide-based field-effect transistors. Following that guidance keeps your novelty in the memory cell rather than adding risk on the readout side.
Why does domain wall pinning matter so much?
It appears in both the Phase I and Phase II task lists, and Phase II says particular attention must be paid to the atomic-scale configuration of the engineered sliding ferroelectric state and the role of domain-wall pinning for controllability. Physically, freely moving walls mean poor retention, while strongly pinned walls mean expensive slow switching. Controlled pinning is the engineering crux.
What does Phase II require?
Integrated sliding-ferroelectric memory-device prototypes and array-level architectures, with systematic evaluation of endurance, switching speed, and energy efficiency under realistic operating conditions. It must address the atomic-scale configuration and domain-wall pinning, address scaling and manufacturability including initial demonstration of wafer-scale patterning of local gates, partitioning of van der Waals structures into individual memory cells, and device packaging of memory arrays, and establish quantitative comparison against competing nonvolatile memory technologies on switching energy, integration density, and intrinsic fatigue resistance.
What are the Phase III applications?
Energy-efficient memory for edge computing, high-density embedded memory, and robust architectures for defense-relevant electronics. As metrics are established, broader applications include neuromorphic and in-memory computing, reconfigurable logic, radiation-tolerant electronics, cryogenic control electronics, and memory integrated with two-dimensional semiconductor platforms. The topic notes the technology may offer relatively low-power and moderate-speed operation, which is a candid hedge worth reading.
Is this MURI-derived work?
Yes. The topic states that recent Department of War investments through the Multidisciplinary University Research Initiative have demonstrated advances in twisted two-dimensional heterostructures into atomically thin twistronic memory cell prototypes with potential advantages in speed, endurance, energy efficiency, and scalability. That provenance is the transition narrative this program exists to fund.
What is a homostructure, and why does the title use that word?
A homostructure stacks the same material against itself, with the moire polarity arising from the twist rather than from a chemical interface between different materials. Twisted bilayer hexagonal boron nitride is the canonical example.
How much funding is available?
The Phase I amount must not exceed $250,000 over a period of 12 months. Phase I awardees may also request up to $6,500 in Technical and Business Assistance, in addition to the cost ceiling and not subject to profit or fee, using the mandatory SBIR/STTR TABA Request Form in Volume 5.
When is the proposal deadline?
The topic opens September 23, 2026 and proposals are due October 21, 2026 through the Defense SBIR/STTR Innovation Portal at dodsbirsttr.mil.
How long can my technical volume be?
Not to exceed 15 pages. Technical volumes exceeding 15 pages will be deemed non-compliant and will not be evaluated, which is stricter than simply disregarding the extra pages. The transition narrative and the preliminary Phase II Plan both count inside that limit.
What extra content does this program require in the technical volume?
Two things beyond the standard DoW STTR Phase I content. A narrative description of how early research in academic labs will be transitioned to the small business via this opportunity. And a preliminary Phase II Plan specifying the overall vision, approach, and potential product proposed at the end of Phase II. Both must fit inside the 15 pages.
Do I need a research institution partner?
Yes. This is an STTR, which requires a formal partnership with a single partnering research institution, with statutory minimum work shares of at least 40 percent by the small business and at least 30 percent by the institution per the DoW STTR Program solicitation. If selected, you must negotiate a written agreement between the small business and the research institution allocating intellectual property rights and rights to carry out follow-on research, development, or commercialization, using the Model Agreement for the Allocation of Rights.
How does the Phase II submission window work?
Phase II proposals may only be submitted by Phase I awardees, and all Phase I awardees are eligible. A 30-day submission window is expected to commence 6 to 9 months into the Phase I period, with details provided by the S&T Foundations STTR Program Management Office. This will be the only opportunity to submit a Phase II proposal for the Basic Research topics, and proposals received outside the established window will not be evaluated.
What does that mean for how I plan Phase I?
You will be writing the Phase II proposal on partial Phase I results, six to nine months into a twelve-month effort. Front-load the work so your most persuasive results land early. The program also says it is vital to discuss Phase I results with your Technical Point of Contact, so establish that relationship early in performance.
How is Phase II funded?
A 10 to 12 month base period not to exceed $1,000,000 plus a 10 to 12 month option period not to exceed $1,000,000, with the entire Phase II effort not exceeding $2,000,000.
How are proposals evaluated?
Against the DoW solicitation criteria, in descending order of importance: technical merit, soundness, and innovation of the proposed approach first, then qualifications of key personnel, then commercialization potential. The evaluation includes an assessment not only of the Phase I feasibility studies but of the overall approach and product proposed at the end of Phase II. Only Government personnel evaluate proposals, except personnel from Strategic Analysis, Inc who provide programmatic and administrative assistance.
Is the Company Commercialization Report evaluated?
No. Completion of the CCR as Volume 4 is required, but information contained in it will not be considered by S&T Foundations during proposal evaluations.
Are there Percentage of Work restrictions?
Yes. Deviations from the Percentage of Work requirements described in the DoW Program BAA are not permitted. With a research institution performing at least 30 percent of the work, model the arithmetic before finalizing the subaward.
What CMMC level applies?
The projected requirement for this topic is CMMC Level 1.
Is this work classified?
No. Phase I and Phase II efforts are expected to be performed at the Unclassified level, and no topic-level ITAR or EAR restriction paragraph appears on this topic or on any of the seven topics in this release.
Can I employ foreign nationals?
If the offeror proposes to employ a foreign national, refer to the DoW Solicitation for definitions and reporting requirements. The unclassified expectation makes this program more compatible with an open university research environment than several other components in this cycle.
Can I request a debriefing if not selected?
Yes. Non-selected proposers may request a written debriefing within 30 calendar days of the select or non-select notification. Debriefs are typically provided in writing via email to the Corporate Official within 30 days of receipt of the request. Oral debriefs may not be accommodated. If the Corporate Official's contact information has changed, a notice on company letterhead signed by that official must accompany the request.
When will I hear back, and who is notified?
Within 90 days of the closing date of the topic, approximately January 19, 2027, through DSIP to both the firm's Corporate Official and the Principal Investigator of record.
Who do I contact with questions?
Technical questions about the topic go through DSIP Topic Q&A, which closes October 7, 2026. Administrative questions about the STTR Program and these proposal preparation instructions go to Jason Day at jason.o.day.civ@mail.mil.
Positioning Advice for Companies Considering This Topic
Map named people onto the four required competencies. The topic states that advancement requires combined expertise in design, fabrication, measurement, and modeling of lattice dynamics in twisted moire structures, plus charge transport and optoelectronics in van der Waals materials. That is a staffing test, key personnel is the second-ranked criterion, and a proposal that leaves one of the four uncovered has a visible hole.
Give a specific domain wall pinning strategy. Pinning appears in both the Phase I and Phase II task lists, and it is the real engineering tension: enough pinning for retention, little enough for cheap fast switching. Nanostructured local gates, deliberate defect placement, strain engineering, or twist-angle gradients are all defensible answers. Hand-waving is not.
Do not over-promise performance numbers. Phase I is explicitly about quantifying the seven indicators to establish the targets for Phases II and III. A proposal that asserts Phase II specifications it cannot yet justify is answering a different question than the one asked. Rigor about how you will measure beats optimism about what you will find.
Use the readout platforms the topic names. Graphene and TMD field-effect transistors are specified because they are well established and scalable. Following that guidance keeps your novelty concentrated in the memory cell where it belongs, and inventing a new readout adds risk the topic did not ask you to take.
Benchmark against real incumbents by name. The topic asks for quantitative comparison against competing nonvolatile memory technologies on switching energy, integration density, and intrinsic fatigue resistance. Name flash, magnetoresistive RAM, resistive RAM, and ferroelectric FETs, and put your projected numbers next to theirs.
Say something credible about wafer scale. Twisted van der Waals stacks are made one at a time by hand, and Phase II asks for wafer-scale patterning of local gates, cell partitioning, and array packaging. Even a partial answer in the preliminary Phase II Plan differentiates you, because this is the barrier between a beautiful physics result and a memory product.
Consider the niche applications, not just the mainstream. The Phase III list includes radiation-tolerant electronics and cryogenic control electronics alongside edge computing and embedded memory. Those niches are where an atomically thin ferroelectric can win without beating commercial memory on cost per bit, and the topic itself concedes the technology may deliver relatively low-power, moderate-speed operation rather than record speed.
Claim the MURI lineage explicitly. The topic says Department of War MURI investments already produced atomically thin twistronic memory cell prototypes. Naming that program, that group, and those people is exactly the transition narrative this program was built to fund.
Write the transition narrative as a real plan, not a paragraph. This program exists to move academic discoveries into small businesses. Whose discovery, moving how, through what mechanism, with what people, and what does the small business own afterward. That narrative is a program requirement and it is where the S&T Foundations mission lives.
Put key personnel forward. Qualifications of key personnel is the second-ranked evaluation criterion, ahead of commercialization potential. On a basic research transition topic, naming the people who actually did the underlying science is worth more proposal space than a market sizing exercise.
Take the preliminary Phase II Plan seriously. The evaluation explicitly assesses the overall approach and product proposed at the end of Phase II, not just the Phase I studies. Fit it to the program's own structure of a base plus option, each 10 to 12 months and each up to $1,000,000, and make the product concrete.
Front-load the Phase I schedule. The Phase II window opens 6 to 9 months in and it is the only one. Whatever a Phase II reviewer needs to see must exist by month six. Say in your Phase I plan what will be complete by then.
Count your pages. Exceeding 15 pages makes the technical volume non-compliant and unevaluated, which is a harsher rule than most components apply, and it applies to a volume that must also contain the transition narrative and the Phase II Plan.
Start the allocation of rights conversation now. A written agreement allocating intellectual property and follow-on rights is required upon selection. On a topic where the core science originates in a university laboratory, that negotiation determines whether you have a commercial product at the end. Do not leave it until award.
Use the debriefing if you lose. A written debrief within 30 days of notification is available on request, and this program recurs. That is cheap, specific feedback most applicants never ask for.
