DON26BZ01-NV024 — 3D-Heterogeneously Integrated Photonic (HIP) Imaging Sensor

Award Maximum: $140,000 (Base) / $100,000 (Option) Period of Performance: 6 months (Base) + 6 months (Option) Phase Type: Phase I

OBJECTIVE: Design, fabricate, and verify the performance of a 3D-heterogeneously integrated photonic (HIP) imaging sensor consisting of a detector array, read-out integrated circuit (ROIC), and photonic transmitter.

DESCRIPTION: Emerging military electro-optical and infrared (EO/IR) sensors enable high resolution through small pixels, wide field-of-view through large arrays, and high frame rate through high sensitivity and low latency. For the most advanced focal plane array (FPA) sensors, the data bandwidth dictated by the high pixel count and bit rate is reaching the limits of conventional copper wire interconnects.

Datalinks using optical interconnects offer a unique and commercially mature solution that can obviate the copper bandwidth limitation, while offering additional advantages of lower power, lower cost, and on-chip integration. For large arrays, the high data rate can be further managed by tiling synchronized, independently addressed smaller arrays, which divides the serialized data stream into multiple parallel paths, while also improving foundry yield.

A photonic layer could be added to create a 3D vertically integrated FPA stack, enabling large arrays to operate at exceptionally high data rates. 3D heterogeneous integration of the FPA stack can be accomplished using bump-bonding, direct-bond integration, or other techniques, but ultra-low capacitance connections are required for low-noise operation to permit the short photon integration times inherent to high-frame-rate imaging.

When tiled in large arrays of small pixels, the 3D-HIP imaging sensor will provide concurrent wide-FOV, high-resolution, and ultra-high frame rate, circumventing conventional imaging sensor paradigms. Frame rate should use 1 KHz as the goal to address high data rate challenges. This SBIR topic's intent is the development and maturation of 3D heterogeneous integration (3DHI) of electrical and optical/photonic layers that achieves high bandwidth interconnection.

PHASE I: Perform a trade study of design variables. Create a concept for a 3D-HIP imaging sensor design. All design features must be supported by quantitative modelling, simulations, or general trade analysis. The design should be adaptable to all EO/IR spectral bands, formats, and pixel sizes. Address detector, ROIC, and photonic layer designs and interconnections. Prepare a Phase II plan that includes the fabrication, integration, and testing strategy.

PHASE II: Fabricate a prototype 3D-HIP imaging sensor based on the Phase I design. It is expected, but not required, that detector, electronic, and photonic layers will be fabricated and integrated at separate foundries. While only a 3D-HIP transmitter is required, the output must be received and processed into imagery. The transmitter chip should be compatible with formation of a tiled array. The transmitter-to-receiver connection should employ optical fiber of nominally 1 meter length. The transceiver performance will be thoroughly documented in the Phase II final report.

PHASE III DUAL USE APPLICATIONS: Support the transition to Navy use. High-resolution, wide-FOV, high-speed imagers will find wide use in many commercial and industrial applications such as computer vision, autonomous navigation, security and industrial facility surveillance monitoring.

KEYWORDS: Sensors, read-out integrated circuit, ROIC, photonics, tiling, chiplet, heterogeneous integration